The higher density per unit area of microelectronic devices on a chip presents a challenge to reduce the parasitic capacitance between the gate conductor line and the metal filled vias that form the contacts to the device source and drain. This unwanted capacitance arises because of the close proximity of the metal filled vias and the gate line and becomes a significant detractor of the device speed when the device pitch is small. An upside-down field effect transistor (“UFET”) is one way to address this challenge. A UFET is able to reduce the capacitance between the gate conductor line and the metal filled vias. An upside-down FET has the additional advantage of maintaining more of the strain induced in the channel by stress liners since the liner is not punctured by the contact via holes.
However, one major issue with known upside-down field effect transistor (UFET) structures is that the back-side contacts to the source and drain are not self-aligned to the source and drain regions of the device. In some proposed structures the contact vias are formed by etching through the source and drain silicon to contact the silicide layer. This presents a problem if the contact holes are misaligned. A failure may occur when part of the contact hole extends over a region not silicided.
There is a need for an improved device design to overcome the above-stated shortcomings of the known art.